The semiconductor or IC industry aims to manufacture ICs with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large scale integration has led to a continued shrinking of circuit dimensions and device features. The ability to reduce the size of structures, such as gate lengths in field-effect transistors and the width of conductive lines, is driven by lithographic performance.
With conventional lithography systems, radiation is provided through or reflected off a mask or reticle to form an image on a semiconductor wafer. Generally, the image is focused on the wafer to expose and pattern a layer of material, such as photoresist material. In turn, the photoresist material is utilized to define doping regions, deposition regions, etching regions, or other structures associated with ICs in one or more layers of the semiconductor wafer. The photoresist material can also define conductive lines or conductive pads associated with metal layers of an IC. Further, the photoresist material can define isolation regions, transistor gates, or other transistor structures and elements.
Older lithography systems are typically configured to expose the photoresist material at a radiation having a wavelength of 248 nanometers (nm). However, because the resolution limit of features is, in part, dependent upon the exposure wavelength, it is desirable to pattern photoresist material using radiation at shorter exposure wavelengths (e.g., the wavelength range bounded approximately by, and including, 193 nm to 13.4 nm (193 nm, 157 nm, 126 nm, or 13.4 nm)). Unfortunately, materials, equipment, and/or fabrication techniques suitable for 248 nm lithography are not generally transferable to shorter exposure wavelengths, and materials, equipment and processes tailored for use with shorter exposure wavelengths are required.
The stability of a developed photoresist pattern can be important in a number of practical semiconductor manufacturing processes, for example, double exposure processes, processes that include an intense ion implantation step, and/or processes that include an intense etching step. In one instance of a double exposure process, the semiconductor wafer is subjected to two lithography sub-processes, where the first developed photoresist pattern must tolerate the application of the second photoresist layer, the exposure of the second photoresist layer, and the development of the second photoresist layer. The chemicals and solvents used during the second lithography sub-process can harm the first developed photoresist pattern, resulting in distortion of the first developed photoresist pattern. Likewise, subjecting a developed photoresist pattern to intense ion implantation and/or intense etching can distort, destroy, melt, or otherwise harm the developed photoresist pattern.